HD64570 Datasheet, PDF (431/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Register
MSCI (Channel 1)
MSCI TX/RX Buffer
Register L Channel 1:
TRBL Channel 1
Address
CPU CPU
Mode Mode
0, 1 2, 3 Remarks
40H 41H
7
6
5
4
3
2
1
0
Async
Byte sync
TRB7 TRB6 TRB5 TRB4 TRB3 TRB2 TRB1 TRB0
Bit sync HDLC (TRBL7)(TRBL6)(TRBL5)(TRBL4)(TRBL3)(TRBL2)(TRBL1)(TRBL0)
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
X
X
X
X
X
X
X
X
MSCI TX/RX Buffer
Register H Channel 1:
TRBH Channel 1
41H 40H
Value written to, or read from, the transmit/receive buffer
7
6
5
4
3
2
1
0
Async
Byte sync
TRB15 TRB14 TRB13 TRB12 TRB11 TRB10 TRB9 TRB8
Bit sync HDLC (TRBH7()TRBH6()TRBH5()TRBH4()TRBH3()TRBH2()TRBH1()TRBH0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
X
X
X
X
X
X
X
X
MSCI Status Register 0 42H 43H
Channel 1: ST0 Channel 1
Value written to, or read from, the transmit/receive buffer
Async
7
6
5
4
3
2
1
0
TXINT RXINT — — — — TXRDYRXRDY
Byte sync
Bit sync HDLC
Read/Write
R
R
————
R
R
Initial value
0
0
0
0
0
0
0
0
TXINT interrupt
0: No interrupt
1: Interruput
RXINT interrupt
0: No interrupt
1: Interruput
TX ready
0: Transmit buffer satisfying
the conditions set by TRC1
1: Transmit buffer satisfying
the conditions set by TRC0
RX ready
0: Receive buffer empty
1: Receive buffer satisfying
the conditions set by RRC
Rev. 0, 07/98, page 415 of 453