HD64570 Datasheet, PDF (228/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

The ADPLL receives the receive data and is supplied with the operating clock. The ADPLL has
two clock input lines: one for the receive baud rate generator output, and the other for the RXC
line input.
The ADPLL uses the receive baud rate generator output or an external clock (RXC line input) as
the operating clock to extract the clock component from the receive data. The ADPLL operating
clock, functioning as a common operating clock, is supplied to the receive data noise suppressor,
clock extractor, and data delay unit. The ADPLL sends the extracted clock and the noise-
suppressed receive data to the receiver. The extracted clock serves as the receive clock. When the
output of the receive baud rate generator is used as the ADPLL operating clock, the RXC line
outputs the receive clock. (ADPLL operation is controlled by the RXCS2−RXCS0 bits of the RX
clock source register (RXS).)
The ADPLL uses the output of the receive baud rate generator as the operating clock to suppress
noise for the receive clock input from the RXC line. The ADPLL operating clock, functioning as
a common operating clock, is supplied to the noise suppressers for the receive clock and the
receive data. In this case, the clock extractor does not operate. The ADPLL sends noise-
suppressed receive data and the receive clock to the receiver.
The clock extraction from the receive data and noise suppression for the receive data and receive
clock are synchronized with the ADPLL operating clock. The ratio of the ADPLL clock rate to
the bit rate can be selected from × 8, × 16, and × 32 using the DRATE1−DRATE0 bits of mode
register (MD2).
The relationship between the ADPLL clock and bit rates is shown in table 5.15.
Table 5.15 Relationship Between the ADPLL Operating Clock and Bit Rates
Function
Clock extraction from receive data
and noise suppression for receive
data
ADPLL Operating
Clock Source
RXC line input
Receive BRG output
Noise suppression for receive clock Receive BRG output
and receive data
Operating
Mode
×8
× 16
× 32
×8
× 16
× 32
Ratio of ADPLL
Operating Clock Rate
to Bit Rate
8/1
16/1
32/1
8/1
16/1
32/1
The ADPLL can compensate the phase of the extracted clock pulses. If the extracted clock is
skewed by one or more cycles from the receive data that was passed via the data delay unit, the
Rev. 0, 07/98, page 212 of 453