HD64570 Datasheet, PDF (142/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Specific values are listed in table 5.21, Register Values and Bit Rates in Asynchronous Mode, and
table 5.22, Register Values and Bit Rates in Byte Synchronous/Bit Synchronous Mode.
5.2.8 MSCI Command Register (CMD)
The command register (CMD) specifies the command for MSCI transmission/reception control.
This is a write-only register and always reads 00H.
Async
7
6
5
4
3
2
1
0
—*1 —*1 _{CMD5 CMD4 CMD3 CMD2 CMD1 CMD0}
Byte sync
Bit sync HDLC
Read/Write
——W
W
WW W W
Initial value
—
———————
Command
• Transmit commands
000001: TX reset
000010: TX enable
000011: TX disable
000100: TX CRC initialization
000101: TX CRC calculation
exclusion
000110: End-of-message
000111: Abort transmission
001000: MP bit on
001001: TX buffer clear
Others: Reserved ^*2
• Receive commands
• Other commands
010001: RX reset
100001: Channel reset
010010: RX enable
110001: Enter search mode
010011: RX disable
000000: No operation
010100: RX CRC initialization
010101: Message reject
010110: Search MP bit
010111: RX CRC calculation
exclusion
011000: Forcing RX CRC
calculation
Notes: 1. Reserved. These bits always read 0 and must be set to 0.
2. When this setting is selected, normal operation is not guaranteed.
Bits 7–6: Reserved. These bits always read 0 and must be set to 0.
Bits 5–0 (CMD5–CMD0: Command): The functions of these bits are described below.
• Asynchronous/Byte synchronous/Bit synchronous mode
Bits 5–0 specify three types of commands: transmit, receive, and other commands. These
commands and their values are described in table 5.1 to table 5.3.
Rev. 0, 07/98, page 126 of 453