HD64570 Datasheet, PDF (58/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

N.C. 67
V _SS
68
SYNC1 69
RTS1 70
DCD1 71
Serial
I/O
CTS1 72
channel ^{RxD1 73}
1
RxC1 74
TxC1 75
TxD1 76
V _SS
77
SYNC0 78
V _CC
79
RTS0 80
Serial
DCD0 81
I/O
channel
CTS0
82
0
RxD0 83
RxC0 84
TxC0 85
TxD0 86
MPU
select
CPU1 87
CPU0 88
Data
Address
44 A21
43 A20
42 A19
41 A18
40 A17
39 A16
38 A15
37 A14
36 A13
35 A12
34
V_CC
33
V_CC
32 A11
31
V_SS
30 A10
29 A9
28 A8
27 A7
26 A6
25 A5
24 A4
23
*3
Interrupt Bus
Bus System
arbitration inter- clock
face
(top view)
Bus interface
Figure 2.2 Pin Arrangement on FP-88
*1: CPU mode 1:
Not used. Open
*2: CPU modes 2, 3:
Not used. Open
*3: Always not used.
Open
Rev. 0, 07/98, page 42 of 453