HD64570 Datasheet, PDF (271/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Reserved. When read, the value of this bit is undefined. This bit can be set to 0 or 1.
• Chained-block transfer mode
The EOME bit enables or disables a DMA frame end interrupt (DMIB) caused by the EOM bit
of DSR as follows:
EOME = 0: Disables an interrupt (DMIB) caused by the EOM bit
EOME = 1: Enables an interrupt (DMIB) caused by the EOM bit
Bit 5 (BOFE: Buffer Overflow/Underflow Interrupt Enable): The function of this bit is
described below.
• Single-block transfer mode
Reserved. When read, the value of this bit is undefined. This bit can be set to 0 or 1.
• Chained-block transfer mode
The BOFE bit enables or disables a buffer overflow/underflow interrupt (DMIA) caused by the
BOF bit of DSR as follows:
BOFE = 0: Disables an interrupt (DMIA) caused by the BOF bit
BOFE = 1: Enables an interrupt (DMIA) caused by the BOF bit
Bit 4 (COFE: Counter Overflow Interrupt Enable): The function of this bit is described
below.
• Single-block transfer mode
Reserved. When read, the value of this bit is undefined. This bit can be set to 0 or 1.
• Chained-block transfer mode
The COFE bit enables or disables a counter overflow interrupt (DMIA) caused by the COF bit
of DSR as follows:
COFE = 0: Disables an interrupt (DMIA) caused by the COF bit
COFE = 1: Enables an interrupt (DMIA) caused by the COF bit
Bits 3–0: Reserved. These bits always read 0 and must be set to 0.
Rev. 0, 07/98, page 255 of 453