HD64570 Datasheet, PDF (303/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

updates BAR and BCR by writing the BP value of the descriptor to BAR, and the BFL value of
the descriptor to BCR. In this way, the DMAC transfers data to the buffers specified by the
descriptors by updating the descriptors.
On detecting the end of a frame in the buffer currently being written, the DMAC immediately
switches the buffer, and writes the MSCI frame status register (FST) value, which is stored
immediately after the data transfer, into the status (ST) field of the corresponding descriptor. (At
this time, the DMAC also writes data length (DL) to the descriptor.) In single-frame transfer
mode, the DMAC terminates data transfer after updating the CDA value. In multi-frame transfer
mode, the DMAC switches the buffer and updates the CDA, BAR, and BCR values, after which
the DMAC starts writing data to the next buffer.
At completion of frame transfer, the DMAC issues interrupt DMIB (if enabled).
EDA must initially contain the low-order 16 bits of the address of the descriptor indicating the first
buffer that is disabled for receive data writing. In this case, buffers can be accessed if the EDA
value is updated, even while DMA is enabled. At this time, EDA must be loaded with the start
address of the descriptor indicating the buffer next to the last write buffer.
When the CDA and EDA values are equal and a transfer request is issued, the DMAC terminates
data transfer and issues interrupt DMIA (if enabled).
Rev. 0, 07/98, page 287 of 453