HD64570 Datasheet, PDF (120/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

is appended to the output data in the TX shift register. The data is then output to the TXD line via
the encoder.
See sections 5.2.1, MSCI Mode Register 0 (MD0), 5.2.2, MSCI Mode Register 1 (MD1), 5.2.4,
MSCI Control Register (CTL), 5.2.18, MSCI Synchronous/Address Register 0 (SA0), and 5.2.19,
MSCI Synchronous/Address Register 1 (SA1), for details on the specification of parity, stop bit
length, and break transmission in asynchronous mode. These sections also contain information on
the specification of SYN characters, aborts, flags, and CRC calculation in byte and bit
synchronous modes.
Each stage of the transmit buffer has 1-bit EOM/MP bit command FIFO. Refer to section 5.3,
Operations. For MP bit transmission in asynchronous mode and EOM transmission in bit
synchronous mode, see section 5.2.8, MSCI Command Register (CMD).
5.2 Registers
The MSCI has 27 registers which select the operating mode (asynchronous, byte synchronous, or
bit synchronous), and control the transmitter, receiver, ADPLL, and baud rate generator. These
registers are accessed with MPU instructions.
For changing the operating mode, these registers must be pre-initialized with a channel reset
command by the command register (CMD).
5.2.1 MSCI Mode Register 0 (MD0)
Mode register 0 (MD0) specifies the operating mode (asynchronous, byte synchronous, or bit
synchronous), CRC calculation expression, and stop bit length for asynchronous mode, and sets
the auto-enable function.
This register is reset under either of the following conditions:
• Hardware reset
• Channel reset command
The receive reset command must be issued immediately after rewriting the contents of MD0,
otherwise the contents of the status register may change especially when the contents of MD0 are
rewritten after being initially set up after power-on or initialization.
Rev. 0, 07/98, page 104 of 453