HD64570 Datasheet, PDF (177/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Bits 7−0 (SA17−SA10: Synchronous/Address): The function of these bits is described below.
• Asynchronous mode
Not used
• Byte synchronous mode
The SA17−SA10 bits specify bits 7−0 of the SYN character pattern for transmission in byte
synchronous mono-sync or byte synchronous external-sync mode, and the high-order eight bits
(bits 15−8) of the SYN character pattern in bi-sync mode.
• Bit synchronous mode
The SA17−SA10 bits set the values shown in table 5.5 according to the address field check
mode selected in HDLC mode. The contents of this register are not used for transmission; the
address must be written in the FIFO.
Table 5.5 SA17−SA10 Function in Bit Synchronous Mode
Mode
HDLC mode
Address Field Check
No address field checked
Single address 1
Single address 2
Dual address
Bits 7−0 of SA1
Not used
Not used
Bits 15−8 of the secondary station address
Bits 15−8 of the secondary station address
Rev. 0, 07/98, page 161 of 453