HD64570 Datasheet, PDF (28/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

1.6.3 MSCI Registers (2)
Address
CPU Modes 0 & 1
CPU Modes 2 & 3
Initial Value at Reset*¹
Read/W
rite
Register Name
Symbol Channel 0 Channel 1 Channel 0 Channel 1 MSB
LSB
TX/RX buffer register
TRBL 20H
40H
21H
41H
× × × × × × × × R/W*³
TRBH 21H
41H
20H
40H
× × × × × × × × R/W*³
RX ready control register RRC 3AH
5AH
3BH
5BH
0 0 0 0 0 0 0 0 R/W
TX ready control register 0 TRC0 38H
58H
39H
59H
0 0 0 0 0 0 0 0 R/W
TX ready control register 1 TRC1 39H
59H
38H
58H
0 0 0 1 1 1 1 1 R/W
Current status register 0 CST0 3CH
5CH
3DH
5DH
0 0 0 0 0 0 0 0 R/W
Current status register 1 CST1 3DH
5DH
3CH
5CH
0 0 0 0 0 0 0 0 R/W
Notes: 1. These initial values apply after a hardware reset or execution of a channel reset
command. Some registers are also initialized to these values by the RX reset command
or TX reset command. See section 5.2, Registers, for details.
2. The functions of some bits vary depending on the operating mode (asynchronous, byte
synchronous, or bit synchronous). See the register descriptions starting in section 5.2.1.
3. The TX/RX buffer register (TRBL, TRBH) acts as the receive buffer register for the
received character when read, and as the transmit buffer register for the transmitted
character when written.
1.6.4 DMAC Registers Common to Channels 0 to 3
Address
CPU Modes CPU Modes ^{Initial Value at Hardware Reset} Read/
0&1
2&3
Write
Register Name Symbol
MSB
LSB
DMA priority control PCR 08H
09H
0 0 0 0 0 0 0 0 R/W
register
DMA master enable DMER 09H
08H
1 0 0 0 0 0 0 0 R/W
register
Note: Use byte access to read and write PCR and DMER. These registers cannot be accessed by
word access.
Rev. 0, 07/98, page 12 of 453