HD64570 Datasheet, PDF (79/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 3.2 Signal Line States in System Stop Mode
Signal Line
A₁−A₇
A₈−A₂₃
BUSY
BEO
RD/NC
WR/R/W
A₀/LDS
BHE/HDS
WAIT
AS
HOLD/BUSREQ
INT
D₀−D₇
D₈−D₁₅
NC: Not connected
CPU Mode 0
Input
High impedance
Input
High output
Input
Input
Input
Input
High output
Input
Low output
High
(open drain)
High impedance
High impedance
Signal Line States
CPU Mode 1
CPU Modes 2, 3
Input
Input
High impedance
High impedance
Input
Input
High output
High output
Input
NC
Input
Input
Input
Input
NC
Input
High output
High output
Input
Input
High output
High output
High
(open drain)
High
(open drain)
High impedance
High impedance
NC
High impedance
3.3 Bus Arbiter
3.3.1 Overview
The SCA is equipped with a bus arbiter which arbitrates bus contention between the on-chip
DMAC and an external bus master device. The on-chip DMAC is connected internally to the bus
arbiter. When the on-chip DMAC requests the bus, the bus arbiter drives BUSREQ active low
(drives HOLD active high in CPU mode 0) to ask the host MPU for control of the bus.
When the host MPU makes BUSACK active low (or makes HOLDA active high in CPU mode 0),
the bus arbiter monitors the BUSY line. If BUSY is high, the bus arbiter takes control of the bus
and drives BUSY low to notify external devices that the SCA is using the bus. The on-chip
DMAC then starts DMA transfer.
If BUSACK goes active low (or HOLDA goes active high in CPU mode 0) when there is no bus
request from the on-chip DMAC, the bus arbiter drives BEO active low to pass the BUSACK
signal (HOLDA in CPU mode 0) on to other bus master devices. BEO can be used for daisy
chaining.
Rev. 0, 07/98, page 63 of 453