HD64570 Datasheet, PDF (130/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

RXCHR1, RXCHR0 = 1, 1: 5 bits/character
• Byte synchronous/Bit synchronous mode
Reserved. These bits always read 0 and must be set to 0.
Bits 1−0 (PMPM1−PMPM0: Parity/Multiprocessor Mode): Specify the multiprocessor (MP)
mode, and whether or not to use the parity check in asynchronous mode. Rewriting these bits
during operation activates the contents of the new setting for subsequent transmit/receive
characters.
• Asynchronous mode
PMPM1, PMPM0 = 0, 0:
Appends no parity/MP bit; performs no parity check
PMPM1, PMPM0 = 0, 1:
Appends an MP bit according to the commands
PMPM1, PMPM0 = 1, 0:
Appends even parity for parity check
PMPM1, PMPM0 = 1, 1:
Appends odd parity for parity check
For the parity check and multiprocessor mode (MP) in asynchronous mode, see Parity /MP Bit,
in section 5.3.1, Asynchronous Mode. For commands, see section 5.2.8, MSCI Command
Register.
• Byte synchronous/Bit synchronous mode
Reserved. These bits always read 0 and must be set to 0.
5.2.3 MSCI Mode Register 2 (MD2)
Mode register 2 (MD2) specifies the transmission/reception data code type, the ratio of the
advanced digital phase locked loop (ADPLL) operating clock to the bit rate, and the connection
between the transmit/receive data and the TXD/RXD lines. For the ADPLL, see section 5.5,
ADPLL.
This register is reset under either of the following conditions:
• Hardware reset
• Channel reset command
Rev. 0, 07/98, page 114 of 453