HD64570 Datasheet, PDF (84/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

CLK (CPU modes 1, 2, 3)
DMA cycle
T_i T₁ T₃
CLK (CPU mode 0)
BUSREQ
(CPU modes 1, 2, 3)
HOLD (CPU mode 0)
BUSACK
(CPU modes 1, 2, 3)
HOLDA (CPU mode 0)
BUSY
Input
Output
Input
BEO
CLK (CPU modes 1, 2, 3)
Slave mode
Master mode
Example a
DMA cycle
T_i T₁ T₃
Slave mode
CLK (CPU mode 0)
BUSREQ
(CPU modes 1, 2, 3)
HOLD (CPU mode 0)
BUSACK
(CPU modes 1, 2, 3)
HOLDA (CPU mode 0)
BUSY
Input
Output
Input
BEO
Slave
mode
Master mode
Example b
Slave mode
Figure 3.6 Bus Arbitration Sequence examples
Rev. 0, 07/98, page 68 of 453