HD64570 Datasheet, PDF (56/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

1.7.14 Timers
The SCA has a built-in four-channel, 16-bit timer module. All channels have identical functions
and specifications. They can be used as interval timers or watchdog timers, or for time-out
detection or other purposes. The timer features are listed below.
• Each timer uses a 16-bit reloadable up-counter.
• The timer increments at a rate of BC/20 to BC/27, where BC is a base clock obtained by
dividing the internal system clock (φ) by eight.
• A counter generates interrupt when it reaches a specified value.
1.7.15 Wait Controller
The SCA has a built-in wait controller. The wait controller can insert wait states to lengthen the
DMA bus cycle.
The address space is divided into three areas (figure 1.28). The number of wait states inserted
when each area is accessed can be set independently in the range from 0 to 7. This enables the
SCA to support memory chips having different access times without requiring external wait
control logic.
Wait states can also be inserted by the WAIT input. In this case there is no limit on the number of
wait states inserted. In cases of conflict between the number of wait states set in the wait control
register and the number requested via the WAIT line, the larger number of wait states is inserted.
FFFFFFH
Physical address
boundary
register 1 (PABR1)
Physical address
boundary
register 0 (PABR0)
Address
PAH area
Wait states
(0 to 7)
Address
PAM area
Wait states
(0 to 7)
000000H
PAL area
Wait states
(0 to 7)
Physical address space
Wait control register H
(WCRH)
Wait control register M
(WCRM)
Wait control register L
(WCRL)
PAH: Physical address high
PAM: Physical address middle
PAL: Physical address low
Figure 1.28 Subdivision of Address Space by Wait Controller and Insertion of Wait States
Rev. 0, 07/98, page 40 of 453