HD64570 Datasheet, PDF (184/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

5.2.22 MSCI RX Ready Control Register (RRC)
The RX ready control register (RRC) determines the MSCI RX ready (RXRDY) activation
condition. The function of this register is the same in asynchronous, byte synchronous, and bit
synchronous modes.
7
Async
—
Byte sync
Bit sync HDLC
Read/Write
—
Initial value
0
6
5
4
3
2
1
0
— — RRC4 RRC3 RRC2 RRC1 RRC0
— — R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
RX ready control (RXF)
Note: Bits 7-5 are reserved. These bits always read 0 and must be set to 0.
Bits 7−5: Reserved. These bits always read 0 and must be set to 0.
Bits 4−0 (RRC4−RRC0: RX Ready Control): Determine the MSCI RX ready (RXRDY)
activation condition. When the data byte count in the receive buffer is equal to or greater than
RXF + 1, that is, the value set by these bits + 1, RX ready is activated. In other words, the
RXRDY bit of status control register 0 (ST0) is set to 1. (The RXRDY bit is set to 0 when there is
no data left in the receive buffer.) Any value can be set in the range from 00H−1FH.
Rev. 0, 07/98, page 168 of 453