HD64570 Datasheet, PDF (161/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

5.2.12 MSCI Status Register 3 (ST3)
Status register 3 (ST3) indicates data transmit status in bit synchronous mode, whether or not the
ADPLL is in search mode in byte or bit synchronous mode, and also indicates the CTS and DCD
line levels and the transmitter/receiver status (enable or disable). This is a read-only register.
The reset descriptions of this register's bits are as follows:
• Bits 5, 3, and 1 are reset by a TX reset command
• Bits 2 and 0 are reset by an RX reset command
• All bits are reset by a hardware reset or a channel reset command
• All bits are reset in system stop mode
No bit of this register generates an interrupt.
Async
7
6
5
4
3
2
1
0
—*1 —^*1 —*1 —*1 CTS DCD TXENBLRXENBL
Byte sync
SRCH
Bit sync HDLC
SLOOP
Read/Write
—— R
R
RR
R
R
Initial value
0
0
0
0
X^*2
X^*2
0
0
Sending on loop
CTS input line status
• Bit synchronous mode 0: CTS low level
0: Transmits no MSCI data 1: CTS high level
TX enable
0: Disable
1: Enable
1: Transmits MSCI data
RX enable
0: Disable
Search mode
• Byte/Bit synchronous mode
1: Enable
0: ADPLL normal mode
1: ADPLL search mode
DCD input line status
0: DCD low level
1: DCD high level
Notes: 1. Reserved. These bits always read 0.
2. Undefined
Rev. 0, 07/98, page 145 of 453