HD64570 Datasheet, PDF (112/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

4.2.9 Interrupt Enable Register 2 (IER2)
The interrupt enable register 2 enables or disables interrupt requests indicated in interrupt status
register 2 (ISR2). IER2 bits 7 to 4 are cleared to 0 at a reset. Bits 3 to 0 are reserved bits that
always read 0. When writing to IER2, write 0 in bits 3 to 0.
7
6
5
4
3
2
1
0
Bit name T3IRQET2IRQET1IRQET0IRQE — —
——
Read/Write R/W R/W R/W R/W — — — —
Initial value
0
0
0
0
0
0
0
0
Timer channel 3
interrupt request enable
0: Disabled
1: Enabled
Timer channel 0
interrupt request enable
0: Disabled
1: Enabled
Timer channel 2
interrupt request enable
0: Disabled
1: Enabled
Timer channel 1
interrupt request enable
0: Disabled
1: Enabled
Note: Initial values are the values after a hardware reset.
Bit 7 (T3IRQE: Timer Channel 3 Interrupt Request Enable):
T3IRQE = 0: The timer channel 3 T3IRQ interrupt is disabled.
T3IRQE = 1: The timer channel 3 T3IRQ interrupt is enabled.
Bit 6 (T2IRQE: Timer Channel 2 Interrupt Request Enable):
T2IRQE = 0: The timer channel 2 T2IRQ interrupt is disabled.
T2IRQE = 1: The timer channel 2 T2IRQ interrupt is enabled.
Rev. 0, 07/98, page 96 of 453