HD64570 Datasheet, PDF (41/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Internal data bus
6
ST2
FST
CST1 CST0
Async
Stop bit Parity/MP
(1)
(1)
TRB
RXD
RXC
RXC
From transmitter
(local loop back)
Receive data
Decoder
(1)
Zero deletion, Synchronous character, Parity, MP bit,
flag, abort, or secondary station or framing error
idle detection address detection
detection
BOP
BOP,
Receive shifCt ^OP
register 1 (8)
BOP, COP
Async
BOP
(CRCCC =
Receive shif^"t^1"
Receive shift
register 2 (8)
register 3 (8)
Status FIFO
Receive buffer _{(32 stages)}
(32-byte FIFO)
(8)
(6)
Receive shift
register 4 (8)
ADPLL
Receive clock
8
Baud rate
generator
To transmitter
(local loop back
and auto echo)
COP, BOP (CRCCC = 0)
BOP
COP
Receive delay
register (8)
8
Receive CRC
shift register (8)
TRB:
ST2:
FST:
CST1, CST0:
‡:
Async:
COP:
BOP:
Receive CRC calculator
(16)
TX/RX buffer register
Status register 2
Frame status register
Current status registers 1 and 0
Receive data flow
Asynchronous mode
Byte-synchronous mode
Bit-synchronous mode
Numbers in parentheses are bit lengths.
Figure 1.13 Block Diagram of the MSCI Receiver
Rev. 0, 07/98, page 25 of 453