HD64570 Datasheet, PDF (226/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Receive
CLK
baud rate
generator
RXC line
f _{BRG =}
f_CLK
TMC
÷ 2^RXBR
ADPLL operating clock
(TMC: 1 to 256,
RXBR: 0 to 9)
f _BR
Receive clock
ADPLL
(Sampling rate:
operating clock
× 8,× 16×, 32)
Noise-suppressed
receive clock
(1/1 clock mode)
f_CLK : System clock (CLK) frequency
(c) Receive Clock Noise Suppression
Figure 5.31 Receive Clock Sources (cont)
5.4.4 Baud Rate Generator
The output frequency of the baud rate generator for transmission and reception is obtained by the
following equation:
f_BRG =
f_CLK
TMC
÷ 2^BR
f_BRG:
f_CLK:
TMC:
BR:
BRG output frequency
System clock frequency
Value (1−256) set in the time constant register (TMC)
Value (0−9) set in the TXBR3−TXBR0 bits of TXS, or the RXBR3−RXBR0
bits of RXS
Frequencies determined by the above equation are independently output for transmission and
reception from the baud rate generator.
5.4.5 ADPLL
In byte or bit synchronous mode, either of two receive clocks can be used for the MSCI: a clock
extracted from the receive data by the ADPLL or the noise-suppressed RXC line input by ADPLL.
The ADPLL has the following operating modes: × 8, × 16, and × 32 (ratio of the ADPLL
operating clock rate to the bit rate). In other words, the operating clock frequency must be 8, 16,
or 32 times the bit rate, to use the ADPLL clock extraction function, regardless of the source of the
operating clock. The DRATE1−DRATE0 bits of mode register 2 (MD2) selects the ADPLL
operating mode.
Rev. 0, 07/98, page 210 of 453