HD64570 Datasheet, PDF (414/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Register
DMAC (General)
DMA Master Enable
Register (DMER)
Not used
Not used
Not used
Not used
Not used
Not used
Interrupt Control
Interrupt Status
Register 0 (ISR0)
Address
CPU CPU
Mode Mode
0, 1 2, 3 Remarks
09H
08H
7
6
Single-block
transfer mode _{DME —}
Chained-block
transfer mode
Read/Write
Initial value
R/W —
1
0
5
4
3
2
1
0
———— ——
——————
0
0
0
0
0
0
0AH
0BH
0CH
0DH
0EH
0FH
0BH
0AH
0DH
0CH
0FH
0EH
DMA master enable
0: Disable
1: Enable
10H 11H
7
6
5
4
3
2
1
0
Bit name TXINT1RXINT1TXRDYR1 XRDY1TXINT0RXINT0TXRDY0RXRDY0
Read/Write
Initial value
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
MSCI channel 1 TXINT
0: Not requested
1: Requested
MSCI channel 1 RXINT
0: Not requested
1: Requested
MSCI channel 1 TXRDY
0: Not requested
1: Requested
MSCI channel 1 RXRDY
0: Not requested
1: Requested
MSCI channel 0 RXRDY
0: Not requested
1: Requested
MSCI channel 0 TXRDY
0: Not requested
1: Requested
MSCI channel 0 RXINT
0: Not requested
1: Requested
MSCI channel 0 TXINT
0: Not requested
1: Requested
Rev. 0, 07/98, page 398 of 453