HD64570 Datasheet, PDF (166/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Bits 5−2: Reserved. These bits always read 0 and must be set to 0.
Bit 1 (TXRDYE: TXRDY Interrupt Enable): The function of this bit is described below.
• Asynchronous/Byte synchronous/Bit synchronous mode
TXRDYE = 0:
Disables an interrupt request set by the TXRDY bit of ST0
TXRDYE = 1:
Enables an interrupt request set by the TXRDY bit of ST0; a TXRDY
interrupt request is issued to the MPU when the TXRDY bit of ST0 is set to 1
Bit 0 (RXRDYE: RXRDY Interrupt Enable): The function of this bit is described below.
• Asynchronous/Byte synchronous/Bit synchronous mode
RXRDYE = 0:
Disables an interrupt request set by the RXRDY bit of ST0
RXRDYE = 1:
Enables an interrupt request set by the RXRDY bit of ST0; a RXRDY
interrupt request is issued to the MPU when the RXRDY bit of ST0 is set to 1
The relationship between the interrupt enable bit and status bit is shown in figure 5.6.
Status bit
Interrupt enable bit
Interrupt request
Figure 5.6 Interrupt Conditions
As shown in figure 5.6, an interrupt request is issued only when both the status bit and the
interrupt enable bit are 1. The same relationship holds true between interrupt enable registers 0−2
(IE0−IE2) and status registers 0−2 (ST0−ST2), and between the frame interrupt enable register
(FIE) and the frame status register (FST).
Rev. 0, 07/98, page 150 of 453