HD64570 Datasheet, PDF (165/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

5.2.14 MSCI Interrupt Enable Register 0 (IE0)
Interrupt enable register 0 (IE0) enables or disables the TXINT, RXINT, TXRDY, and RXRDY
interrupt requests. Interrupt requests are issued to the MPU when both the status register 0 (ST0)
bits and the corresponding bits of this register are set to 1. For details on interrupts, see section
5.7, Interrupts.
7
6
5
4
3
2
1
0
Async
Byte sync
TXINTERXINTE ^{— — — —} TXRDYERXRDYE
Bit sync HDLC
Read/Write R/W R/W — —
— — R/W R/W
Initial value
0
0
0
0
0
0
0
0
TXINT interrupt
enable
0: Disable
1: Enable
RXINT interrupt
enable
0: Disable
1: Enable
TXRDY interrupt
enable
0: Disable
1: Enable
RXRDY interrupt
enable
0: Disable
1: Enable
Note: Bits 5–2 are reserved. These bits always read 0 and must be set to 0.
Bit 7 (TXINTE: TXINT Interrupt Enable): The function of this bit is described below.
• Asynchronous/Byte synchronous/Bit synchronous mode
TXINTE = 0: Disables an interrupt request set by the TXINT bit of ST0
TXINTE = 1: Enables an interrupt request set by the TXINT bit of ST0; a TXINT interrupt
request is issued to the MPU when the TXINT bit of ST0 is set to 1
Bit 6 (RXINTE: RXINT Interrupt Enable): The function of this bit is described below.
• Asynchronous/Byte synchronous/Bit synchronous mode.
RXINTE = 0: Disables an interrupt request set by the RXINT bit of ST0
RXINTE = 1: Enables an interrupt request set by the RXINT bit of ST0; a RXINT interrupt
request is issued to the MPU when the RXINT bit of ST0 is set to 1
Rev. 0, 07/98, page 149 of 453