HD64570 Datasheet, PDF (147/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

5.2.9 MSCI Status Register 0 (ST0)
Status register 0 (ST0) indicates the status of interrupts (TXINT and RXINT) and the
transmit/receive buffer. When any bit of this register is set to 1, an MPU interrupt request is
generated (if enabled).
This register is reset under either of the following conditions:
• Hardware reset
• Channel reset command
• System stop mode
Async
7
6
5
TXINT RXINT —^*1
Byte sync
Bit sync HDLC
Read/Write
R
R
—
Initial value
0
0
0
4
—^*1
—
0
3
2
1
0
—*1 —*1 TXRDYRXRDY
—— R
R
0
0
0
0
TXINT interrupt
0: No interrupt
1: Interruput
TX ready
0: Transmit buffer satisfies
the conditions set by TRC1^*2
1: Transmit buffer satisfies
the conditions set by TRC0 ^*3
RXINT interrupt
0: No interrupt
1: Interruput
RX ready
0: Receive buffer empty
1: Receive buffer satisfies
the conditions set by RRC ^{*4, *5}
Notes: ^{1. Reserved. These bits always read 0.}
2. TRC14–TRC10 bits of TX ready control register 1 (TRC1)
3. TRC04–TRC00 bits of TX ready control register 0 (TRC0)
4. RRC4–RRC0 bits of RX ready control register (RRC)
5. In bit synchronous mode, RXRDY is set to 1 when data with EOM enters the
receive buffer.
Rev. 0, 07/98, page 131 of 453