HD64570 Datasheet, PDF (40/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

1.7.8 Receiver
The receiver (figure 1.13) converts serial receive data into parallel data according to the selected
communication format. The LSB of the data is received first. The data are shifted through a
succession of receive shift registers, the last of which is the eight-bit receive shift register 4
(figure 1.12).
Zero deletion, flag,
abort, or idle detection
Detect secondary
station address
To receive FIFO
BOP
Receive shift register 1 Receive shift register 2 Receive shift register 3 Receive shift register 4with
CRC
Internal receive
data (NRZ)
CRC calculator
Receive
data
Decoder
Receive
clock
Zero deletion, flag,
abort, or idle detection
Detect secondary
station address
Receive shift register 1 Receive shift register 2
To receive FIFO
Receive shift register 4
BOP
withou
CRC
Detect SYN character
To receive FIFO
Receive shift register 1 Receive shift register 2
Receive shift register 4
8
Receive delay register
8
Receive CRC
shift register
CRC calculator
Detect parity/MP bit
and framing errors
To receive FIFO
Stop bit Parity/MP bit
Receive shift register 4
Figure 1.12 Receive Data Path (in each protocol mode)
COP
Async
Rev. 0, 07/98, page 24 of 453