HD64570 Datasheet, PDF (320/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

TCNTH
7
6
5
4
3
2
1
0
Read/Write
Initial value
Timer
R/W
0
2¹⁵
R/W
0
2¹⁴
R/W
0
2¹³
R/W
0
2¹²
R/W
0
2¹¹
R/W
0
2¹⁰
R/W
0
2⁹
R/W
0
2⁸
TCNTL
7
6
5
4
3
2
1
0
Read/Write
Initial value
Timer
R/W
0
2⁷
R/W
0
2⁶
R/W
0
2⁵
R/W
0
2⁴
R/W
0
2³
R/W
0
2²
R/W
0
2¹
R/W
0
2⁰
CPU Mode
C
Mode 0
4
Mode 1
5
Mode 2
6
Mode 3
5
Note: Initial values are the same in system stop mode and after reset.
7.2.2 Timer Constant Register (TCONR: TCONRH, TCONRL)
The timer constant register (TCONR), provided for each of channels 0, 1, 2, and 3, specifies timer
output timing. The TCONR value is constantly compared with the timer up-counter (TCNT)
value. When they match, the CMF bit of timer control status register (TCSR) is set to 1, and an
interrupt is generated, if enabled. Here, TCNT is cleared and resumes incrementing from 0000H.
(For details on timing, see section 7.3.2, Output Timing.) In this way, periodic interrupts can be
generated without software overhead. TCONR is initialized to FFFFH at reset or in system stop
mode.
Rev. 0, 07/98, page 304 of 453