HD64570 Datasheet, PDF (170/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

5.2.16 MSCI Interrupt Enable Register 2 (IE2)
Interrupt enable register 2 (IE2) enables or disables interrupt requests when the status bits of status
register 2 (ST2) are set to 1. For details on interrupts, see section 5.7, Interrupts.
Async
Byte sync
7
6
5
4
3
2
1
0
— * PMPE PEE FRMEEOVRNE — * — * — *
—* —* —*
CRCEE
Bit sync HDLC EOME SHRTE ABTE RBITE
Read/Write R/W R/W R/W R/W R/W R/W — —
Initial value
0
0
0
0
0
0
0
0
EOM interrupt enable
• Bit synchronous mode
0: Disable
1: Enable
FRME interrupt enable
• Asynchronous mode
0: Disable
1: Enable
CRCE interrupt enable
• Byte/Bit synchronous mode
0: Disable
1: Enable
PMP interrupt enable
• Asynchronous mode
0: Disable
1: Enable
SHRT interrupt enable
• Bit synchronous mode
0: Disable
1: Enable
RBIT interrupt enable
• Bit synchronous mode
0: Disable
1: Enable
OVRN interrupt enable
0: Disable
1: Enable
PE interrupt enable
• Asynchronous mode
0: Disable
1: Enable
ABT interrupt enable
• Bit synchronous mode
0: Disable
1: Enable
Note: The bits marked with * are reserved. These bits always read 0 and must be set to 0.
Rev. 0, 07/98, page 154 of 453