HD64570 Datasheet, PDF (311/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Register and Descriptor Setting: To start an MSCI-to-memory chained-block transfer, follow
the steps below starting with the DMA in its initial state. (Steps 1 to 7 may be completed in any
order.)
1. Create any desired number of descriptors anywhere in the system area (64 Kbytes or less),
using the MPU. Note that since the high-order eight bits of the 24-bit address are specified by
CPB, the high-order eight bits are common to the same 64-Kbyte area. Specify a 16-bit chain
pointer (CP) and a 24-bit buffer pointer (BP) in each descriptor. (Descriptors may be specified
in DMA halt state.)
2. Set the TMOD bit of DMR to 1.
3. Clear the NF bit of DMR to 0 for single-frame transfer, and set the NF bit to 1 for multi-frame
transfer.
4. Load the high-order eight bits of the 24-bit descriptor address into CPB.
5. Load the low-order 16 bits of the start address of the descriptor corresponding to the buffer
next to the last write-enabled buffer into EDA.
6. Load the start address of the descriptor corresponding to the first receive buffer into CDA.
7. Load the buffer length in byte units into BFL. (This value is shared by all buffers.)
8. After steps 1 to 7, set the DE bit of DSR to 1 to start DMA operation.
External Bus Timing: In MSCI-to-memory chained-block transfer mode, one byte or one word
of data is transferred within one memory write cycle. The memory write cycle timing is the same
as that in MSCI-to-memory single-block transfer mode shown in figure 6.11.
Prior to the start of DMA transfer and at buffer switching, this transfer mode requires several set-
up cycles for the DMAC to perform a read operation on a descriptor and other operations, as
shown in figure 6.22. In the figure, 18 states (CPU modes 0, 2, and 3) or 23 states (CPU mode 1)
are inserted before the start of a DMA transfer. At buffer switching, 8 states (CPU modes 0, 2,
and 3) or 11 states (CPU mode 1) indicated by “*3” are inserted to write receive data length (DL)
and status (ST) fields in the descriptor. This is followed by a read operation on the next
descriptor.
Rev. 0, 07/98, page 295 of 453