HD64570 Datasheet, PDF (175/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Bits 7−0 (SA07−SA00: Synchronous/Address): The function of these bits is described below.
• Asynchronous mode
Not used
• Byte synchronous (mono- or bi-sync) mode
The SA07−SA00 bits specify bits 7−0 of the SYN character pattern for reception in mono-sync
mode, and the low-order eight bits (bits 7−0) of the SYN character pattern for transmission and
reception in bi-sync mode.
• Bit synchronous mode
The SA07−SA00 bits set the values shown in table 5.4 according to the address field check
mode selected in HDLC mode. The contents of this register are not used for transmission; the
address must be written in the FIFO.
Table 5.4 SA07−SA00 Function in Bit Synchronous Mode
Mode
HDLC mode
Address Field Check
No address field checked
Single address 1
Single address 2
Dual address
Bits 7−0 of SA0
Not used
Bits 7−0 of the secondary station address
Not used
Bits 7−0 of the secondary station address
When using a two-octet SYN character pattern or address, the first and second octets of data must
be set in SA0 and SA1, respectively (figure 5.7).
(1) BOP (dual address)
Header
Flag A1
A2
C
↑
↑
SCA register · · · · · · · · · · SA0 SA1
I
FCS Flag
(2) COP (bi-sync mode)
Header
SYN1
↑
SCA register · · · SA0
SYN2
↑
SA1
Data
CRC
Figure 5.7 MSCI Synchronous/Address Registers (SA0 and SA1) and Two-Octet Data
Rev. 0, 07/98, page 159 of 453