HD64570 Datasheet, PDF (295/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 6.6 shows a memory-to-MSCI chained-block multi-frame transfer using four descriptors and
four buffers. In this example, data is added to the buffer during transmission. As described in the
table, after steps 1 and 2, the MPU writes additional transmit data to buffers 2 and 3 and at the
same time updates EDA to the start address of the descriptor indicating buffer 0. In this way, the
DMAC transfers the data in buffers 2 and 3 after the data in buffer 1. Since the DMAC remains
enabled after one frame has been transferred in multi-frame transfer mode, some frame end
interrupts (DMIB) remain unprocessed. The number of unprocessed interrupts is stored in the
frame end interrupt counter (FCT). When the FCT value is 1111 and frame transfer continues, a
counter overflow error occurs and the DMAC terminates data transfer after transmitting the
current frame. The FCT value is then reset to 0000, and a DMIA interrupt is generated (if
enabled). For details, see sections 6.2.8, DMA Mode Register (DMR), and 6.2.9, Frame End
Interrupt Counter (FCT).
Table 6.6 Memory-to-MSCI Chained-Block Multi-Frame Transfer Mode (transmit data
added during transmission)
DMAC
Step Operation
MPU
CDA EDA DE Bit
Operation Value Value Value Note
1
—
A₀ ‡ CDA A₀
A₂
1
A₂ ‡ EDA
1 ‡ DE bit
Specifies the buffer containing
data to be transmitted using CDA
(see figure 6.16)
2
Reads data —
from buffer 0
A₀
A₂
1
3
A₁ ‡ CDA
—
A₁
A₂
1
4
—
Loads
A₁
A₃
1
transmit data
into buffer 2
A₃ ‡ EDA
5
—
Loads
A₁
A₀
1
transmit data
into buffer 3
A₀ ‡ EDA
6
Reads data —
from buffer 1
A₁
A₀
1
Adds transmit data to the buffer,
and rewrites EDA.
7
A₂ ‡ CDA
—
A₂
A₀
1
A_n: Start address of each descriptor
CDA: Current descriptor address register
EDA: Error descriptor address register
DE bit: Bit 1 of the DMA status register (DSR)
(see figure 6.16)
Rev. 0, 07/98, page 279 of 453