HD64570 Datasheet, PDF (92/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

3.4.3 Master Mode Bus Cycle
In master mode (DMA mode), data moves from memory to the SCA in a read cycle, and from the
SCA to memory in a write cycle. The address and bus interface signals are output signals, except
for WAIT which is an input signal.
Word Transfer from Odd Address: In CPU modes 0, 2, and 3, DMA transfer of a word starting
at an odd address is performed as two byte transfers. The DMAC first transfers one byte from the
odd address, then transfers the remaining byte from the succeeding even address. Figure 3.13
shows how a word is transferred from an odd address.
D₁₅
D₈ D₇
D₀
D₁₅
D₈ D₇
D₀
2n + 3
—
Next transfer 2n + 2 2n + 2 Next transfer
—
2n + 3
2n + 1 First transfer
—
2n
2n
—
First transfer 2n + 1
(a) CPU Mode 0
(b) CPU Modes 2 and 3
2n, 2n + 1, ^… are addresses
Figure 3.13 Word Transfer from Odd Address
Word Transfer from Even Address: In CPU modes 0, 2, and 3, a word is transferred from an
even address by direct memory access in a single word transfer operation.
Rev. 0, 07/98, page 76 of 453