HD64570 Datasheet, PDF (442/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Register
MSCI (Channel 1)
MSCI TX Ready Control
Register 1 Channel 1:
TRC1 Channel 1
Address
CPU CPU
Mode Mode
0, 1 2, 3 Remarks
59H 58H
7
6
5
4
3
2
1
0
Async
— — — TRC14 TRC13 TRC12 TRC11 TRC10
Byte sync
Bit sync HDLC
Read/Write
—
—
— R/W R/W R/W R/W R/W
Initial value
0
0
0
1
1
1
1
1
MSCI RX Ready Control
Register Channel 1:
RRC Channel 1
5AH 5BH
TX ready control 1
7
6
5
4
3
2
1
0
Async
— — — RRC4 RRC3 RRC2 RRC1 RRC0
Byte sync
Bit sync HDLC
Read/Write
—
—
— R/W R/W R/W R/W R/W
Initial value
0
0
0
0
0
0
0
0
Not used
MSCI Current Status
Register 0 Channel 1:
CST0 Channel 1
MSCI Current Status
Register 1 Channel 1:
CST1 Channel 1
Not used
Not used
5BH 5AH
5CH 5DH
RX ready control
Async
Byte sync
7
6
5
4
3
2
1
— PMPC0 PEC0 FRMEC0OVRNC0 —
—
———
CRCEC0
Bit sync HDLC EOMC0SHRTC0ABTC0 RBITC0
Read/Write
R
R
R
R
R
R—
Initial value
0
0
0
0
0
0
0
0
CDE0
R
0
5DH 5CH
Data status in the top stage of the receive buffer
Current data 0
0: No data exists
1: Data exists
Async
Byte sync
7
6
5
4
3
2
1
— _{PMPC1 PEC1 FRMEC1OVRNC1} —
—
———
CRCEC1
Bit sync HDLC EOMC1SHRTC1ABTC1 RBITC1
Read/Write
R
R
R
R
R
R
–
Initial value
0
0
0
0
0
0
0
0
CDE1
R
0
5EH 5FH
5FH 5EH
Data status in the second stage of the receive buffer
Current data 1
0: No data exists
1: Data exists
Rev. 0, 07/98, page 426 of 453