HD64570 Datasheet, PDF (230/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

5 Receive
clock noise
suppression
Operating
mode
× 8 x<1/8
1/8≤x<2/8
2/8≤x
Clock
extractor
does not
function for
receive
clock noise
suppres-
sion
× 16 x<2/16 2/16≤x<3/16 3/16≤x
× 32 x<4/32 4/32≤x<5/32 5/32≤x
6 Maximum bit Operating
rate for receive mode
clock noise
suppression
×8
1.25 Mbps
× 16
0.62 Mbps
× 32
0.31 Mbps
(x: Noise width/1-bit cell width)
Note: The ADPLL enters search mode when an enter-search-mode command is issued. For
details, see section 5.5.3, Enter-Search-Mode Command.
5.5.2 Operation
The ADPLL has two main functions: clock component extraction from noise-suppressed receive
data, and receive clock noise suppression.
Clock Component Extraction from Receive Data: The flow of receive data and the ADPLL
operating clock signals for clock extraction are shown in figure 5.33. Either the receive baud rate
generator output from clock line 1 or the external clock (RXC line input) from clock line 2 can be
used as the ADPLL clock.
Rev. 0, 07/98, page 214 of 453