HD64570 Datasheet, PDF (397/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

10.4.2 Master Mode Bus Timing
T₁
T₂
T_W
T₃
CLK
BHE, A ₀
A₁– A ₂₃
AS (ME)
WAIT
RD
t _CLAV
t _CHLL
t _AVAL
t_ASWH
t _RYLCL
t _CLRL
t _ASWL
t _CHRYX
t _RYHCH
t _CLLH
t _LLAX
t _CHRYX
t_CLRH
D₀ – D₁₅
t _DVCL
t _RDX
Figure 10.5 Master Mode Read Timing
(CPU Mode 0) (Memory ‡ SCA)
Rev. 0, 07/98, page 381 of 453