HD64570 Datasheet, PDF (339/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Wait Control Register H (WCRH): Specifies the number of wait states to be inserted in a
memory cycle when the PAH area is accessed.
Bit name
Read/Write
Initial value
7
6
5
4
3
2
1
0
—
— — — — PAHW2 PAHW1 PAHW0
— — — — — R/W R/W R/W
0
0
0
0
0
1
1
1
PAH area wait
Note: Bits 7–3 are reserved. These bits always read 0 and must be set to 0.
Bits 7−3: Reserved. These bits always read 0 and must be set to 0.
Bits 2−0 (PAHW2−PAHW0: PAH Area Wait): The functions of these bits are described
below.
PAHW2, PAHW1, PAHW0 = 0, 0, 0: Number of wait states = 0
PAHW2, PAHW1, PAHW0 = 0, 0, 1: Number of wait states = 1
PAHW2, PAHW1, PAHW0 = 0, 1, 0: Number of wait states = 2
PAHW2, PAHW1, PAHW0 = 0, 1, 1: Number of wait states = 3
PAHW2, PAHW1, PAHW0 = 1, 0, 0: Number of wait states = 4
PAHW2, PAHW1, PAHW0 = 1, 0, 1: Number of wait states = 5
PAHW2, PAHW1, PAHW0 = 1, 1, 0: Number of wait states = 6
PAHW2, PAHW1, PAHW0 = 1, 1, 1: Number of wait states = 7
Note that PAHW2, PAHW1, and PAHW0 are initialized to (1, 1, 1) at reset.
8.3 Operation
8.3.1 Wait State Insertion Using the WAIT Line
Wait states can be inserted between states T₂ and T₃ of states T₁−T₃ of a DMA bus cycle, using the
WAIT line.
Rev. 0, 07/98, page 323 of 453