HD64570 Datasheet, PDF (462/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Register
DMAC (Channel 2)
DMA Mode Register
Channel 2: DMR
Channel 2
Address
CPU CPU
Mode Mode
0, 1 2, 3 Remarks
7
6
5
4
3
2
1
0
D1H D0H
Single-block
transfer mode _—
Chained-block
—
— TMOD —
—
CNTE —
transfer mode
NF
Read/Write
Initial value
— — — R/W — R/W R/W —
0
0
0
0
0
0
0
0
Not used
Frame End Interrupt
Counter Channel 2: FCT
Channel 2
DMA Interrupt Enable
Register Channel 2:
DIR Channel 2
DMA transfer mode
0: Single-block transfer
1: Chained-block transfer
Number of DMA frames
• Chained-block transfer
0: Single frame
1: Multi-frame
D2H D3H
Frame end interrupt counter (FCT)
enable/disable
• Single-block transfer
Set this bit to 0
• Chained-block transfer
0: Frame end interrupt counter (FCT) disabled
1: Frame end interrupt counter (FCT) enabled
D3H D2H
7
6
Single-block
transfer mode _{— —}
Chained-block
transfer mode
Read/Write
Initial value
——
0
0
5
4
3
2
1
0
— — ——
——
FCT3 FCT2 FCT1 FCT0
——
R
R
R
R
0
0
0
0
0
0
D4H D5H
Frame end interrupt counter (FCT) value
7
6
5
4
3
2
Single-block
transfer mode
— ——
Chained-block ^EOTE
——
transfer mode
EOME BOFE COFE
1
0
——
Read/Write R/W R/W R/W R/W — — — —
Initial value
0
0
0
0
0
0
0
0
Transfer end interrupt
enable
0: Disable
1: Enable
Counter overflow
interrupt enable
• Chained-block transfer mode
0: Disable
1: Enable
Frame transfer end interrupt
enable
• Chained-block transfer mode
0: Disable
1: Enable
Buffer overflow/underflow
interrupt enable
• Chained-block transfer mode
0: Disable
1: Enable
Rev. 0, 07/98, page 446 of 453