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HD64570 Datasheet, PDF (248/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor
Table 5.21 Register Set Values and Bit Rates in Asynchronous Mode (cont)
Bit Rate
(bps)
fCLK (MHz)
12
TMC BR CM Deviation (%)
38400 



19200 39
0
1/16 0.16
9600 39
0
1/32 0.16
4800 39
0
1/64 0.16
2400 39
1
1/64 0.16
1200 39
2
1/64 0.16
600
39
3
1/64 0.16
300
39
4
1/64 0.16
150
39
5
1/64 0.16
110
213 3
1/64 0.03
TMC: Value of the TMC7−TMC0 bits of TMC
BR: Value of the TXBR3−TXBR0 bits of TXS or the RXBR3−RXBR0 bits of RXS
CM: Value of the BRATE1−BRATE0 bits of MD1 (clock mode in asynchronous mode (bit
rate/clock frequency))
Rev. 0, 07/98, page 232 of 453