HD64570 Datasheet, PDF (174/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

5.2.18 MSCI Synchronous/Address Register 0 (SA0)
Synchronous/address register 0 (SA0) specifies the SYN character pattern for reception in byte
synchronous mono-sync mode, the low-order eight bits of the SYN character pattern for
transmission and reception in byte synchronous bi-sync mode, and the secondary station address in
bit synchronous mode. This register is not used in asynchronous or byte synchronous external-
sync mode.
7
6
5
4
3
2
1
0
Async
— ———————
Byte sync
SA07 SA06 SA05 SA04 SA03 SA02 SA01 SA00
Bit sync HDLC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial/value
1
1
1
1
1
1
1
1
SYN pattern for reception/address field check
• Byte synchronous mode
Mono-sync
Bi-sync
External-sync
SYN pattern for reception
SYN pattern for transmission and reception (bits 7–0)
Not used
• Bit synchronous mode
No address field checked
HDLC ^{Single address 1}
mode _{Single address 2}
Dual address
Not used
Bits 7–0 of the secondary station address
Not used
Bits 7–0 of the secondary station address
Note: This register is not used in asynchronous mode.
Rev. 0, 07/98, page 158 of 453