HD64570 Datasheet, PDF (286/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

CLK
T₁
T₂ (T_W) T₃
BHE, A ₀
A₁ to A ₂₃
Memory address
D₀ to D₁₅
Write data
AS
WR
CLK
T₁
T₂ (T_W) T₃
A₀ to A ₂₃
Memory address
D₀ to D₇
Write data
AS
WR
(a) CPU Mode 0
CLK
T₁
T₂ (T_W) T₃
(b) CPU Mode 1
A₁ to A ₂₃
Memory address
D₀ to D₁₅
Write data
AS
R/W
HDS,
LDS
(c) CPU Modes 2 and 3
Figure 6.12 External Bus Timing in MSCI-to-Memory Single-Block Transfer Mode
Rev. 0, 07/98, page 270 of 453