HD64570 Datasheet, PDF (241/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

5.6 Baud Rate Generator
5.6.1 Overview
The MSCI uses an internal baud rate generator (BRG) to generate the MSCI transmit/receive
clock. The BRG has the following main features:
• Output clock frequency range from f_CLK to f_CLK/2¹⁷ (2¹⁷ = 131,072).
(f_CLK: System clock frequency). When f_BRG = f_CLK, BRG output cannot be obtained from the
TXD or RXD lines.
• Frequency accuracy within ±0.5% for any frequency range from f_CLK/100 to f_CLK/2¹⁷.
f − f_BRG ≤ 50 ÷ set value in the time constant register (TMC) (%), where f is the target
frequency and f_BRG is the BRG output frequency set to the value closest to f (f_CLK ≥ f ≥ f_CLK/2¹⁷).
Independent transmit and receive frequencies can be specified as 2ⁿ (where n is a positive
integer).
Figure 5.43 is the baud rate generator block diagram.
BRG
1/1 to
CLK
Reload ^1/256
timer
Divider
8
RX clock source register
RXBR
(RXS)
10 ^Receive
BRG output
selector
1/2⁰ to
1/2 ¹⁷
BRG output
(for reception)
10 ^Transmit
BRG output
selector
1/2⁰ to
1/2 ¹⁷
BRG output
(for transmission)
TMC
Time constant register
(TMC)
TXBR
TX clock source register
(TXS)
CLK: System clock
Figure 5.43 Baud Rate Generator Block Diagram
Rev. 0, 07/98, page 225 of 453