HD64570 Datasheet, PDF (156/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

7
6
5
4
3
2
1
0
Async
— * PMP PE FRME OVRN — ^* — ^* — ^*
Byte sync
—* —* —*
CRCE
Bit sync HDLC EOM SHRT ABT RBIT
Read/Write R/W R/W R/W R/W R/W R/W — —
Initial value
0
0
0
0
0
0
0
0
Receive end of message
• Bit synchronous mode
0: Receive frame end
not detected
1: Receive frame end
detected
Parity/MP bit
• Asynchronous mode
0: Parity/MP bit = 0
1: Parity/MP bit = 1
Short frame
• Bit synchronous mode
0: Normal end of frame
1: Short frame detected
Framing error
CRC error
• Asynchronous mode
• Byte/Bit synchronous mode
0: No framing error
0: No CRC error detected
detected
1: CRC error detected
1: Framing error
detected
Overrun error
0: No overrun error detected
Residual bit frame 1: Overrun error detected
• Bit synchronous
mode
0: Normal end of
frame
1: Residual bit frame
detected
Parity error
• Asynchronous mode
0: No parity error detected
1: Parity error detected
Abort end frame
• Bit synchronous mode
0: Normal end of frame
1: Frame with abort end detected
Note: The bits marked with * are reserved. These bits always read 0 and can be set to 0 or 1.
Bit 7 (EOM: Receive End of Message): Indicates whether or not a receive frame has ended in
bit synchronous mode. This bit is cleared when 1 is written to this bit position.
• Asynchronous/Byte synchronous mode
Reserved. This bit always reads 0 and can be set to 0 or 1.
• Bit synchronous mode
The EOM bit indicates whether or not a receive frame has ended. When the CRCCC bit of
mode register 0 (MD0) is 1, the EOM bit is set to 1 by the last character in the I field of the
receive frame. When the CRCCC bit of MD0 is 0, the EOM bit is set to 1 by the last character
of FCS. Also, when the receive frame end status indicates either a short frame, residual bit
frame, or abort, the EOM bit is set to 1.
Rev. 0, 07/98, page 140 of 453