HD64570 Datasheet, PDF (96/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

CLK
DMA read cycle
T₁
T₂
T₃
DMA write cycle
T₁
T₂
T₃
A₁to A₂₃
AS
HDS, LDS
Memory address
Memory address
WAIT
CLK
R/W
D₀ to D₁₅
(Out)
D₀ to D₁₅
(In)
Receive data
Transmit data
Data
latch point
No T _W states
DMA read cycle
DMA write cycle
T₁
T₂
T_W T₃
T₁
T₂
T_W
T₃
A₁to A₂₃
AS
HDS, LDS
Memory address
Memory address
WAIT
R/W
D₀ to D₁₅
(Out)
D₀ to D₁₅
(In)
Receive data
Transmit data
Data
latch point
With T_W states
Figure 3.17 Master Mode Bus Timing Sequence in CPU Modes 2 and 3
Rev. 0, 07/98, page 80 of 453