HD64570 Datasheet, PDF (167/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

5.2.15 MSCI Interrupt Enable Register 1 (IE1)
Interrupt enable register 1 (IE1) enables or disables interrupt requests when the status bits of status
register 1 (ST1) are set to 1. For details on interrupts, see section 5.7, Interrupts.
Async
Byte sync
Bit sync
HDLC
Read/Write
Initial value
7
6
5
4
3
2
1
0
— * IDLE — * — * CCTSECDCDEBRKDEBRKEE
UDRNE
CLMDESYNCDE
—* —*
FLGDE
ABTDE IDLDE
R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
BRKD interrupt enable
IDL interrupt enable
0: Disable
1: Enable
CCTS interrupt
enable
0: Disable
1: Enable
• Asynchronous mode
0: Disable
1: Enable
ABTD interrupt
enable
CLMD interrupt enable
• Byte/Bit synchronous mode
0: Disable
• Bit sychronous mode
0: Disable
1: Enable
1: Enable
CDCD interrupt enable
UDRN interrupt enable
SYNCD interrupt enable ^{0: Disable}
• Byte/Bit synchronous mode • Byte synchronous mode ^{1: Enable}
BRKE interruput enable
• Asynchronous mode
0: Disable
0: Disable
0: Disable
1: Enable
1: Enable
1: Enable
FLGD interrupt enable
• Bit synchronous mode
0: Disable
1: Enable
IDLD interrupt enable
• Bit synchronous mode
0: Disable
1: Enable
Note: The bits marked with * are reserved. These bits always
read 0 and must be set to 0.
Rev. 0, 07/98, page 151 of 453