HD64570 Datasheet, PDF (50/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

1.7.11 Descriptor Structure
Figure 1.22 shows the structure of a descriptor. Descriptors are allocated in memory in different
ways, depending on the CPU mode.
Address Bit 7
Bit 0
2n + 9
2n + 8
Reserved ^(Note)
Status (ST) 8 bits
2n + 7
Data length H (DLH) 8 bits
2n + 6
2n + 5
Data length L (DLL) 8 bits
Reserved ^(Note)
2n + 4
Buffer pointer B (BPB) 8 bits
2n + 3 Buffer pointer H (BPH) 8 bits
2n + 2
Buffer pointer L (BPL) 8 bits
2n + 1 Chain pointer H (CPH) 8 bits
2n
Chain pointer L (CPL) 8 bits
1. CPU Mode 1
Address Bit 15
Bit 8 Bit 7
Bit 0
2n + 9
2n + 7
2n + 5
Reserved ^(Note)
Data length H (DLH)
Reserved ^(Note)
Status (ST)
Data length L (DLL)
Buffer pointer B (BPB)
2n + 3
Buffer pointer H (BPH)
Buffer pointer L (BPL)
2n + 1
Chain pointer H (CPH)
Chain pointer L (CPL)
2. CPU Mode 0
Address
2n + 8
2n + 6
2n + 4
2n + 2
2n
Address Bit 15
Bit 8 Bit 7
Bit 0
2n + 8
2n + 6
Reserved ^(Note)
Data length H (DLH)
Status (ST)
Data length L (DLL)
2n + 4
2n + 2
Buffer pointer H (BPH)
Reserved ^(Note)
Buffer pointer L (BPL)
Buffer pointer B (BPB)
2n
Chain pointer H (CPH)
Chain pointer L (CPL)
3. CPU Modes 2, 3
Address
2n + 9
2n + 7
2n + 5
2n + 3
2n + 1
Note:
Reserved fields in descriptors are not written by the DMAC, but retain their previous
values. The MPU may write in these fields, but this does not affect the DMAC.
Descriptors must start at an even address (2n). Correct operation is not assured if a
descriptor starts at an odd address.
Figure 1.22 Descriptor Structure
Rev. 0, 07/98, page 34 of 453