HD64570 Datasheet, PDF (137/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

5.2.5 MSCI RX Clock Source Register (RXS)
The RX clock source register (RXS) specifies the receive clock source and the baud rate of the
baud rate generator (BRG) in the receiver. For the baud rate generator, see section 5.6, Baud Rate
Generator.
This register is reset under either of the following conditions:
• Hardware reset
• Channel reset command
Async
Byte sync
Bit sync HDLC
Read/Write
Initial value
7
6
5
4
3
2
1
0
—^*1 _{RXCS2 RXCS1 RXCS0 RXBR3 RXBR2 RXBR1RXBR0}
— R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
Receive clock source
000: RXC line input
010: RXC line input (noise suppression)
100: Internal baud rate generator (BRG) output
110: ADPLL output
(BRG output for ADPLL operating clock)
111: ADPLL output
(RXC line input for ADPLL operating clock)
Others: Reserved ^*2
Receiver baud rate
• Clock division ratio
0000: 1/1
0001: 1/2
0010: 1/4
0011: 1/8
0100: 1/16
0101: 1/32
0110: 1/64
0111: 1/128
1000: 1/256
1001: 1/512
Others: Reserved ^*2
Notes: 1. Reserved. This bit always reads 0 and must be set to 0.
2. Reserved. When these settings are selected, normal operation is not guaranteed.
Rev. 0, 07/98, page 121 of 453