HD64570 Datasheet, PDF (324/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

7.3 Operation Timing
7.3.1 Timer Increment Timing
Figure 7.1 shows the timer increment timing when the counter operating rate is BC. Incrementing
is initiated when a 1 is written to the TME bit of the timer constant/status register (TCSR), after
the timer up-counter (TCNT) and the timer constant register (TCONR) have been set.
When the TCNT and TCONR values match, the CMF bit of TCSR is set to 1, and an interrupt
(T0IRQ, T1IRQ, T2IRQ, or T3IRQ), if enabled, is generated. The CMF bit can be cleared when
TCNT is read after TCSR. (Other instructions can be inserted between the TCSR and TCNT read
instructions.) Here, TCNT is initialized to 0000H, and incrementing restarts. TCNT can be
written even during incrementing. In this case, incrementing restarts from the newly written
value.
When the TME bit is cleared during incrementing, TCNT stops incrementing, retaining its current
contents. When the TME bit is again set to 1, incrementing resumes from the retained value.
Rev. 0, 07/98, page 308 of 453