HD64570 Datasheet, PDF (115/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

CLK (CPU
mode 0)
CLK (CPU
modes 1, 2, 3)
INT
Interrupt
acknowledge cycle
INTA
WAIT
D₀ to D₇
(Out)
Vector address
Figure 4.2 Timing Sequence of Single Acknowledge Cycle
CLK (CPU
mode 0)
CLK (CPU
modes 1, 2, 3)
INT
First interrupt
acknowledge cycle
Second interrupt
acknowledge cycle
INTA
WAIT
D₀ to D₇
(Out)
Vector address
Figure 4.3 Timing Sequence of Double Acknowledge Cycle
Rev. 0, 07/98, page 99 of 453