HD64570 Datasheet, PDF (467/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Register
DMAC (Channel 3)
Frame End Interrupt
Counter Channel 3: FCT
Channel 3
Address
CPU CPU
Mode Mode
0, 1 2, 3 Remarks
F3H F2H
7
6
Single-block
transfer mode
Chained-block
—
—
transfer mode
5
4
3
2
1
0
— — ——
——
FCT3 FCT2 FCT1 FCT0
Read/Write
Initial value
————
R
R
0
0
0
0
0
0
R
R
0
0
Frame end interrupt counter (FCT) value
DMA Interrupt Enable
Register Channel 3: DIR
Channel 3
F4H F5H
7
6
5
4
3
2
Single-block
transfer mode
— ——
Chained-block ^EOTE
——
transfer mode
EOME BOFE COFE
1
0
——
Read/Write R/W R/W R/W R/W — — — —
Initial value
0
0
0
0
0
0
0
0
Transfer end interrupt
enable
0: Disable
1: Enable
Counter overflow
interrupt enable
• Chained-block transfer mode
0: Disable
1: Enable
Frame transfer end interrupt
enable
• Chained-block transfer mode
0: Disable
1: Enable
Buffer overflow/underflow
interrupt enable
• Chained-block transfer mode
0: Disable
1: Enable
Rev. 0, 07/98, page 451 of 453