HD64570 Datasheet, PDF (57/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Section 2 Pin Arrangements and Functions
2.1 Pin Arrangements
Figures 2.1 and 2.2 show the pin arrangements of the SCA chip in QFJ (PLCC (CP-84)) and QFP
(FP-88) packages, respectively.
Bus
interface
Bus Bus
System inter- arbitra-
clock face tion Interrupt
A ₄ 12
A ₅ 13
A ₆ 14
A ₇ 15
A ₈ 16
A ₉ 17
A ₁₀
18
V _SS 19
Address ^A 11
20
V _CC 21
V _CC 22
A ₁₂
23
A ₁₃
24
A ₁₄
25
A ₁₅
26
A ₁₆
27
A ₁₇
28
A ₁₈
29
A ₁₉
30
A ₂₀
31
A ₂₁
32
74 CPU0
73 CPU1
72 TXD0
71 TXC0
70 RXC0
69 RXD0
68 CTS0
67 DCD0
66 RTS0
65 V_CC
64 SYNC0
63 V_SS
62 TXD1
61 TXC1
60 RXC1
59 RXD1
58 CTS1
57 DCD1
56 RTS1
55 SYNC1
54 V_SS
MPU
select
Serial I/O
channel 0
Serial I/O
channel 1
Data
CP-84
(top view)
*1: CPU mode 1:
Not used. Open
*2: CPU modes 2, 3:
Not used. Open
Figure 2.1 Pin Arrangement of CP-84
Rev. 0, 07/98, page 41 of 453