SH7211 Datasheet, PDF (973/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 21 Flash Memory
21.8 Supplementary Information
21.8.1 Specifications of the Standard Serial Communications Interface in Boot Mode
The boot program activated in boot mode communicates with the host via the on-chip SCI of the
LSI. The specifications of the serial communications interface between the host and the boot
program are described below.
(1) States of Boot Program
The boot program has three states.
1. Bit-rate matching state
In this state, the boot program adjusts the bit rate to match that of the host. When the chip
starts up in boot mode, the boot program is activated and enters the bit-rate matching state, in
which it receives commands from the host and adjusts the bit rate accordingly. After bit-rate
matching is complete, the boot program proceeds to the inquiry-and-selection state.
2. Inquiry-and-selection state
In this state, the boot program responds to inquiry commands from the host. The device, clock
mode, and bit rate are selected in this state. After making these selections, the boot program
enters the programming/erasure state in response to the transition-to-programming/erasure
state command. The boot program transfers the erasure program to RAM and executes erasure
of the user MAT and user boot MAT before it enters the programming/erasure state.
3. Programming/erasure state
In this state, programming/erasure are executed. The boot program transfers the program for
programming/erasure to RAM in line with the command received from the host and executes
programming/erasure. It also performs sum checking and blank checking as directed by the
respective commands.
Figure 21.19 shows the flow of processing by the boot program.
Rev. 2.00 May. 08, 2008 Page 949 of 1200
REJ09B0344-0200