SH7211 Datasheet, PDF (133/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 6 Interrupt Controller (INTC)
6.3.4 IRQ Interrupt Request Register (IRQRR)
IRQRR is a 16-bit register that indicates interrupt requests from external input pins IRQ7 to IRQ0.
If edge detection is set for the IRQ7 to IRQ0 interrupts, writing 0 to the IRQ7F to IRQ0F bits after
reading IRQ7F to IRQ0F = 1 cancels the retained interrupts.
IRQRR is initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
0
- IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
0
0
0
0
0
0
0
0
0
R R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Note: * Only 0 can be written to clear the flag after 1 is read.
Bit
Bit Name
15 to 8 ⎯
Initial
Value R/W
All 0 R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 May. 08, 2008 Page 109 of 1200
REJ09B0344-0200