SH7211 Datasheet, PDF (302/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 8 Bus State Controller (BSC)
8.5.7 Burst ROM (Clock Asynchronous) Interface
The burst ROM (clock asynchronous) interface is used to access a memory with a high-speed read
function using a method of address switching called burst mode or page mode. In a burst ROM
(clock asynchronous) interface, basically the same access as the normal space is performed, but
the 2nd and subsequent access cycles are performed only by changing the address, without
negating the RD signal at the end of the 1st cycle. In the 2nd and subsequent access cycles,
addresses are changed at the falling edge of the CK.
For the 1st access cycle, the number of wait cycles specified by the W3 to W0 bits in CSnWCR is
inserted. For the 2nd and subsequent access cycles, the number of wait cycles specified by the W1
to W0 bits in CSnWCR is inserted.
In the access to the burst ROM (clock asynchronous), the BS signal is asserted only to the first
access cycle. An external wait input is valid only to the first access cycle.
In the single access or write access that does not perform the burst operation in the burst ROM
(clock asynchronous) interface, access timing is same as a normal space. In addition, there are
some restrictions on 16-byte write access. For details, see section 8.6, Usage Notes.
Table 8.15 lists a relationship between bus width, access size, and the number of bursts. Figure
8.32 shows a timing chart.
Table 8.15 Relationship between Bus Width, Access Size, and Number of Bursts
Bus Width
8 bits
Access Size
8 bits
16 bits
32 bits
16 bytes
16 bits
8 bits
16 bits
32 bits
16 bytes
CSnWCR. BST[1:0] Bits Number of Bursts Access Count
Not affected
1
1
Not affected
2
1
Not affected
4
1
00
16
1
01
4
4
Not affected
1
1
Not affected
1
1
Not affected
2
1
00
8
1
01
2
4
10*
4
2
2, 4, 2
3
Rev. 2.00 May. 08, 2008 Page 278 of 1200
REJ09B0344-0200